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- Start date: 02/2017
- End date: TBD
- PI: Kindratenko
- Users: kindr, rrthakk2, hequ2
- Objective: Study OpenCL FPGA design flow. Port sample applications and evaluate design flow maturity and ease of use.
- Platform(s): Ac33
- Current status
- 03/09/17: Work in progress. hequ2 and rrthakk2 are re-working two different applications to OpenCL.
- Open issues
- need license to compile for actual hardware