Date: Fri, 29 Mar 2024 08:17:10 -0500 (CDT)
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Evaluation of OpenCL design flow for Altera/Intel FPGAs
Evaluation of OpenCL design flow for Altera/Intel FPGAs
Evaluation of OpenCL design flow for Alte=
ra/Intel FPGAs
- People
- PI: Kindratenko
- Users: kindr, rrthakk2, hequ2
- Dates
- Start date: 02/2017
- End date: TBD
- Platform(s)
- Description
- Objective
- Study OpenCL FPGA design flow. Port sample applications and evaluate de=
sign flow maturity and ease of use.
- Abstract
- Status
- 03/09/17
- Work in progress. hequ2 and rrthakk2 are re-working on two differe=
nt applications to OpenCL.
- 05/16/17
- Open issues
- need license to compile for actual hardware
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