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Evaluation of OpenCL design flow for Altera/Intel FPGAs

  • People
    • PI: Kindratenko
    • Users: kindr, rrthakk2, hequ2
  • Dates
    • Start date: 02/2017
    • End date: TBD
  • Platform(s)
  • Description
    • Objective
      • Study OpenCL FPGA design flow. Port sample applications and evaluate design flow maturity and ease of use.
    • Abstract
  • Status
  • Open issues
    • need license to compile for actual hardware

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