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Evaluation of OpenCL design flow for Altera/Intel FPGAs

  • People
    • PI: Kindratenko
    • Users: kindr, rrthakk2, hequ2
  • Dates
    • Start date: 02/2017
    • End date: TBD
  • PI: Kindratenko
    • Users: kindr, rrthakk2, hequ2
  • Platform(s)
  • DescriptionObjective:
    • Objective
          • Study OpenCL FPGA design flow. Port sample applications and evaluate design flow maturity and ease of use.
      • Platform(s): Ac33
        • Abstract
      • StatusCurrent status
        • 03/09/17:
          • Work in progress.
            hequ2
          •  hequ2 and rrthakk2 are re-working on two different applications to OpenCL.
        • Open issues
          • need license to compile for actual hardware