Energy efficiency of High Performance Computing (HPC) systems is becoming a major concern not only for reasons of energy conservation, failures, and cost reduction, but also because such systems are soon reaching the limits of power available to them. The overall objectives of this research are (i) balance performance/utilization with energy efficiency (i.e., reduce energy consumption with no o little penalty in the performance), and (ii) implement application- and workload-aware power management strategies.
Besides the energy footprint of HPC systems, massive parallelism, scalability and programmability at extreme scales are important challenges towards exascale. We propose using Partitioned Global Address Space (PGAS) programming models and perform power management at the runtime level (i.e., at no cost for the programmer) and target both HPC clusters/supercomputers and many-core systems (i.e., Intel SCC). PGAS assumes a global memory address space that is logically partitioned and a portion of it is local to each processor. PGAS reduces significantly the task of the programmer while it scales for HPC systems (e.g., IBM Bluegene).
Existing energy-efficient runtime implementations for HPC systems mainly focus on applying DVFS during the slack observed in MPI programs. In contrast to PGAS applications, MPI programs are many times difficult to program efficiently. However, in PGAS the message passing is implicit, which requires novel solutions for runtime power management. We studied different HPC kernels (e.g., NAS Parallel Benchmarks) and observed that in PGAS dynamic voltage and frequency scaling can be used effectively (i.e., reducing energy footprint with no or little delay penalty) during (i) synchronization calls (i.e., load imbalance, barriers) and (ii) remote memory accesses.